Conventionally, switch mode DC-DC power converters, such as “buck” converters have output filters to maintain output voltage ripple within an acceptable range. Referring to FIG. 1, a buck topology DC-DC power converter 100 conventionally has an input voltage source 101, a series power switch 102, and an output voltage averaging filter 110. Filter 110 consists of inductor 105 in series with a load (not shown), and capacitor 107, in parallel with the load.
Referring still to FIG. 1, series power switch 102 alternates connection of output averaging filter 110 between the two sides (VIN and common) of input voltage source 101. As illustrated in FIG. 2, filter 110 substantially suppresses the periodic components of the switching waveform, yielding an approximately DC voltage equivalent to the time average of the input voltage multiplied by the duty cycle of power switch 102. The time constant of filter 110 determines attenuation of the periodic switching waveform frequency components, whereas the output impedance of filter 110 is determined by the relative values of inductor 105 and capacitor 107. A choice of filter components represents a compromise between the size and cost of the constituent components and the filter response.
Referring still to FIG. 2, under steady-state conditions of continuous inductor conduction, current through inductor 105 increases during period TON, when the power switch 102 connects filter 110 to VIN, and decreases during the remainder of TPERIOD, when switch 102 connects filter 110 to circuit common.
Referring now to FIG. 3, a buck topology DC-DC power converter 300 may be configured with MOSFET switch 302 and voltage rectifier (diode) 303. In the illustrated configuration, where voltage rectifier 303 includes only a passive diode, current can only flow through the inductor 105 into the output. When the magnetic field in inductor 105 reaches zero, the voltage drop across inductor 105 collapses and diode 303 blocks reverse current.
Continuous inductor conduction requires a minimum output load current for any combination of input voltage, output voltage, and duty-cycle. Referring now to FIG. 4, a configuration is illustrated where voltage rectifier 403 includes switch 403A, capable of conducting current in both the first and third quadrants, in parallel with diode 403B. In the illustrated configuration, inductor 105 can conduct reverse currents from output capacitor 107 back to the common, and therefore support both zero and negative average output current each cycle.
Voltage ripple across output capacitor 107 may be determined from the observation that for half of the TON, and half of the TOFF periods, inductor current exceeds IOUT. During these time intervals, charge accumulates on output capacitor 107, increasing the output voltage from its minimum to maximum value. The current into output capacitor 107 consists of two components:                1. Integral over the interval t from TON/2 to TON of: (VIN−VOUT)/L dt        2. Integral over the interval t from TON to TOFF/2 of: TON*(VIN−VOUT)/(2*L)−(VOUT1/L)dt,        where, VOUT1 is the sum of the output voltage and any voltage drop across switch 102A.        
The voltage developed across output capacitor 107 is the sum of the total charge, i.e., the time integral of current, deposited on output capacitor 107 during these two intervals divided by its capacitance. For the ideal case where VOUT1=VOUT and there are no dissipative losses:VRIPPLE=(TON2*(VIN−VOUT)+2*TOFF*TON*(VIN−VOUT)−TOFF2*VOUT)/(8*L*C)VRIPPLE=TPERIOD2/(8*L*C)*VOUT*(1−VOUT/VIN)
From the above equations, it may be observed that VRIPPLE approaches zero as VOUT either approaches zero or approaches VIN, while the maximum ripple occurs when VOUT=0.5*VIN.
In typical DC-DC converter applications, acceptable output ripple is a defined fraction of the output voltage. Conventionally, selection of the L-C filter time constant is based on the acceptable output ripple for the worst-case condition of the idealized converter where:VRIPPLE—MAXIMUM/VOUT=TPERIOD2/(16*L*C)L*C/TPERIOD2=VOUT/(16*VRIPPLE)
In cases where the duty-cycle is restricted to operate only above 50%, or only below 50%, the value of L*C ratio to TPERIOD2 may be reduced to satisfy the worst-case which will be the duty-cycle value closest to 50%.
DC-DC converters may be used in photovoltaic (PV) applications to condition the output of photovoltaic strings or substrings. In such applications, additional requirements for acceptable output ripple, distinct from those described above, may apply. These requirements may vary depending on whether a DC-DC converter conditions the output of each PV module/sub-string in a given string as opposed to when DC-DC converters are selectively installed only between some modules/sub-strings and the PV string.
Referring now to FIG. 5, a configuration is illustrated in which an output of each and every PV substring/module 511 . . . 515 in PV string 500 connects to a respective DC-DC converter 521 . . . 525. Ripple voltages 531 . . . 535 from each converter 521 . . . 525 add through string 500, as does the output impedance 541 . . . 545 of each converter 521 . . . 525. The input impedance 551 of a load inverter 550 attenuates the voltage ripple seen at load inverter 550 as the ratio of the impedance 551 divided by the sum of DC-DC converter output impedances 541 . . . 545, and the string wiring impedance 590. Where the noise voltage of each DC-DC converter is uncorrelated, noise voltage adds statistically as the root mean square sum. As a result, a string with sixteen DC-DC converters exhibits an RMS ripple noise four times the ripple of a single converter.
Referring now to FIG. 6, a more typical PV string configuration is illustrated. PV string 600 is configured such that only some of the PV substrings/modules (for example, PV substring 511, connected to DC-DC converter 521) are “buffered” (i.e., have an output connected to a DC-DC converter). An output of at least one other PV substring (for example, PV substring 515) is “unbuffered” (i.e., has an output connected directly to string 600). For such configurations, cumulative DC-DC converter ripple voltage divides between the DC-DC converter output impedances, (for example, 541), wiring impedance 590, inverter input impedance 551, and the effective PV substring/module impedance (for example, 545) of each substring connected directly to the string at a particular DC current operating point.
PV substring/module impedance 545 as a function of DC current is very non-linear. The equivalent impedance of a PV cell typically varies from a minimum value at the open circuit voltage (VOC) to a much higher value at short circuit current. Ripple voltage from DC-DC converter 521 modulates the voltage operating point of unbuffered PV substrings/modules (for example, 515). In the normal operating region of a PV substring, near its maximum power point (“MPP”), such modulation reduces the harvestable power from the raw PV substrings/modules. For example, as illustrated in FIG. 7, power output percentage of MPP for mono and multi-crystalline silicon solar cells typically remain at or above 99% only while peak-to-peak ripple is not greater than 6% of VOC. These same cells typically hold at or above 97% only while peak-to-peak ripple is not greater than 11% of VOC.
For a string composed of PV substrings/modules of the same or similar VOC characteristics, that include both DC-DC converter buffered, and unbuffered substrings/modules, the relationship between individual DC-DC converter ripple and VMPP modulation of the unbuffered substrings/modules is:VRIPPLE—RMS—EACH—MODULE=X0.5*VRIPPLE—DC—DC/(N−X)
Where:
N is the number of substrings/modules in the string.
X is the number of DC-DC converter buffered modules.
VRIPPLE—DC—DC is the peak to peak ripple voltage at the output of each converter.
VRIPPLE—RMS reaches a maximum at X=N−1 of:VRIPPLE—RMS=(N−1)0.5*VRIPPLE—DC—DC 
A further consideration is the interaction between maximum power point (MPP) control in each DC-DC converter and an MPP control loop of load inverter 510. Referring now to FIG. 8, inverter MPP regulation algorithms are conventionally designed to detect MPP as a relatively sharp peak in power as a function of, for example, current as illustrated by curve 801. A fully buffered PV string presents the central inverter with a very different transfer function depicted by curve 802. An ideal DC-DC converter transforms input power to output power at negligibly low, and, therefore, effectively constant, loss. As a result, the power versus current curve is flattened for currents greater than MPP. Such a broad, flat response can destabilize the MPP control loop of load inverter 510, resulting in oscillations that periodically take operation beyond the flat section to the sharp power inflection just before load current rises to the point that output power abruptly collapses.
Thus, improved techniques for regulating switch mode DC DC power converter output voltage are needed.